The power cycling of high power semiconductor devices operating at a large percentage of their power handling capability is extremely stressful on the materials of which the device is constructed. The typical high power device will only complete a few thousand power cycles when operated at 100% of its rated power. Operating at this power level implies that the change in temperature (.DELTA.T) from junction to heat sink is on the order of 125.degree. C. This fact limits the practical operating range for acceptable life to approximately a .DELTA.T of 25.degree. to 50.degree. C. The net result is a substantial increase in the cost-per-watt of power conditioning systems, increased system size and lower efficiency. All of these are inconsistent with the needs of industrial power electronics and its technology vector. For the purposes of general discussion herein, the power MOSFET is referred to as a generic high power high frequency device.
It is shown in FIG. 1, and it was designed in the 1950s to hold a pair of semiconductor diodes as a replacement for a vacuum tube rectifier. The bolt pattern is the same as an octal tube socket bolt pattern and the two pins (gate and source) fit the pin 2 and pin 7 location for that same socket. For many years this was the ultimate high power solid state device package. Unfortunately, virtually every aspect of this package is at variance with what is required for modern high power high frequency devices. The two pins which provide highly inductive, 20-30 nH, connections to the interior of the package exit into the heat sink. This has never been a good topology for a high power high speed device. The case (drain), by default, is electrically a very active node, thus requiring an electrical insulator which causes a loss of thermal performance. The case (drain) aspect of this topology also creates a large drain to ground parasitic capacitance. The mismatch in Thermal Coefficient of Expansion (TCE) is large, often requiring buffering materials further degrading the thermal performance.
Furthermore I have observed that there are three factors which combine to cause warping of the package and a loss of thermal contact and therefore an increase in temperature and mechanical die stress as well as a further loss in power handling capability. They are as follows; (1) the package 12 is rigidly attached to the heat sink 15 with the two screws as shown in FIG. 1; (2) the heat sink and the device case are made of different materials with very different TCEs, and (3) the applied power which induces a substantial thermal gradient, .DELTA.T. The die 10 is attached to the upper surface of package 12 by solder 11. An insulator 13 is disposed between the package 12 and the heat sink 15. A thermal compound 14 is disposed on the upper surface of the heat sink. Warping of the package 12 results in a gap or void 16 as shown in FIG. 1.
Approximately thirty years after the development of the device of FIG. 1, a modern RF 0.5 in. flange package shown in FIG. 2. The resemblance to the device of FIG. 1 is clear. Although this package is much less inductive (3-6 nH), it suffers from many of the same mechanical and thermal shortcomings. The die 10 is soldered to a thick BeO substrate 12A (0.064 in. thick). The BeO is attached to a thick copper foot 12B (0.097 in. thick). This results in two solder layers, a thick BeO layer, a thick copper layer, and finally a thin layer of thermal compound 14. As with the device of FIG. 1, the heat sink attachment method also has the potential for warping the case. This is mitigated by the thick BeO layer. However, the penalty for this is a substantial increase in the thermal resistance junction to heat sink (R.sub..theta.JHS) and a commensurate drop in power handling capability.
There has not heretofore been provided a packaging system for high-power semiconductor devices which minimizes or reduces thermal induced stress which results from high-power operation, which also increases power handling capability.